![Figure 2 from A 3.6 mW, 90 nm CMOS Gated-Vernier Time-to-Digital Converter With an Equivalent Resolution of 3.2 ps | Semantic Scholar Figure 2 from A 3.6 mW, 90 nm CMOS Gated-Vernier Time-to-Digital Converter With an Equivalent Resolution of 3.2 ps | Semantic Scholar](https://d3i71xaburhd42.cloudfront.net/48bdec60d749fff1871bec16259275729d3c41be/2-Figure2-1.png)
Figure 2 from A 3.6 mW, 90 nm CMOS Gated-Vernier Time-to-Digital Converter With an Equivalent Resolution of 3.2 ps | Semantic Scholar
![Figure 11 from A Multi-Path Gated Ring Oscillator TDC With First-Order Noise Shaping | Semantic Scholar Figure 11 from A Multi-Path Gated Ring Oscillator TDC With First-Order Noise Shaping | Semantic Scholar](https://d3i71xaburhd42.cloudfront.net/fc336fa24145e8240b65c34f37612e7bdc21e1dc/6-Figure11-1.png)
Figure 11 from A Multi-Path Gated Ring Oscillator TDC With First-Order Noise Shaping | Semantic Scholar
![Figure 3 from A 14-Bit, 1-ps resolution, two-step ring and 2D Vernier TDC in 130nm CMOS technology | Semantic Scholar Figure 3 from A 14-Bit, 1-ps resolution, two-step ring and 2D Vernier TDC in 130nm CMOS technology | Semantic Scholar](https://d3i71xaburhd42.cloudfront.net/687e990ebc74fa5a90abdd6f090e0151104ce5c7/2-Figure3-1.png)
Figure 3 from A 14-Bit, 1-ps resolution, two-step ring and 2D Vernier TDC in 130nm CMOS technology | Semantic Scholar
![Figure 8 from An area efficient asynchronous gated ring oscillator TDC with minimum GRO stages | Semantic Scholar Figure 8 from An area efficient asynchronous gated ring oscillator TDC with minimum GRO stages | Semantic Scholar](https://d3i71xaburhd42.cloudfront.net/0913c067e2f1be0efc54937c0062e79774085541/3-Figure8-1.png)
Figure 8 from An area efficient asynchronous gated ring oscillator TDC with minimum GRO stages | Semantic Scholar
Synthesizable 2D Vernier TDC based on gated ring oscillators Sestavljivi 2D Vernier TDC na osnovi obročnih oscilatorjev
![Figure 1 from An area efficient asynchronous gated ring oscillator TDC with minimum GRO stages | Semantic Scholar Figure 1 from An area efficient asynchronous gated ring oscillator TDC with minimum GRO stages | Semantic Scholar](https://d3i71xaburhd42.cloudfront.net/0913c067e2f1be0efc54937c0062e79774085541/1-Figure1-1.png)
Figure 1 from An area efficient asynchronous gated ring oscillator TDC with minimum GRO stages | Semantic Scholar
![Sensors | Free Full-Text | A Cyclic Vernier Two-Step TDC for High Input Range Time-of-Flight Sensor Using Startup Time Correction Technique Sensors | Free Full-Text | A Cyclic Vernier Two-Step TDC for High Input Range Time-of-Flight Sensor Using Startup Time Correction Technique](https://www.mdpi.com/sensors/sensors-18-03948/article_deploy/html/images/sensors-18-03948-g005.png)
Sensors | Free Full-Text | A Cyclic Vernier Two-Step TDC for High Input Range Time-of-Flight Sensor Using Startup Time Correction Technique
![Electronics | Free Full-Text | Radiation Assessment of a 15.6ps Single-Shot Time-to-Digital Converter in Terms of TID Electronics | Free Full-Text | Radiation Assessment of a 15.6ps Single-Shot Time-to-Digital Converter in Terms of TID](https://pub.mdpi-res.com/electronics/electronics-08-00558/article_deploy/html/images/electronics-08-00558-g001-550.jpg?1571553748)